The invention relates to a method for manufacturing a semiconductor device having a multi-layered wiring interconnection structure.
In a semiconductor integrated circuit, a number of circuit elements are formed on a semiconductor substrate in a limited surface area making it impossible to connect the circuits with planar wiring interconnection techniques. Therefore, multi-layered wiring structures have been employed.
FIGS. 1A-1D are a series of cross-sectional views of a semiconductor device having a conventional multi-layered wiring structure and showing steps in the method employed for producing this structure. In FIG. 1A, a silicon oxide layer 2 is formed on a surface of a semiconductor substrate 1. On the oxide layer 2, an aluminum layer 3 is vapor-deposited which forms a first wiring metal layer. Then, a resist pattern 4 is formed on portions of the aluminum layer 3 which are to be left for forming the interconnection wiring layers photolithographically. FIG. 1A shows this state.
Thereafter, the aluminum layer 3 is etched using the resist layer 4 as a mask after which the mask is removed leaving the wiring layer 3a of aluminum as shown in FIG. 1B. A silicon oxide layer 5 is then formed on the silicon oxide layer 2 and the wiring layer 3a using a CVD technique. The device at this stage is shown in FIG. 1C.
Thereafter, an aluminum layer 6 which forms a second wiring metal layer is vapor-deposited on the silicon oxide layer 5. In this case, since a recessed portion is formed in the silicon oxide layer 5 due to the existence of the wiring layer 3a, the aluminum layer 6 has a tendency to crack around the recessed portion as shown in FIG. 1D, the crack being indicated by reference numeral 6a. These cracks 6a may cause breaking of the wiring layers. For this reason, the yield of such products is considerably lowered due to breaking of the wiring layers before use or the breaking of the wiring layers after long periods of use due to electromigration.